Basically, DDS can be found in a lot of applications such as cellular base stations, wireless local loop base stations, cellular phone, and test and measurement equipment. Since it is digital, the thermal drift susceptibility is the least concern to a design which is favorable to most of the designers. Hence, the adaptivity and flexibility of DDS make it ideal for not only radio frequency but also for many applications. Even digital modulation is possible since the processing signal is in digital. The trade-off of price and space requirement in a design must be made.īy programming the DDS, the desired frequency hopping, numerous modulation formats, and data rates can be achieved. Company like Analog Devices who has been the leader in DDS market offers a dedicated DDS IC with minimum requirement of digital signal processing (DSP) that fit the customer’s need, while Xilinx, Altera, and other companies offer the solution through programmable synthesis. In addition, a process architecture like system in package (SiP), system on a chip (SoC), and 3D stacked die also helps in providing DDS as a solution to complex design such as modulators, local oscillator (LO) clock, and chirp generator. Of course, these will not come true without the advances in IC fabrication technology. For instance, a complete DDS has both DDS core and digital-to-analog converter (DAC) integrated into single package. All of them were integrated together to provide a complete solution to customer with reasonable price. The DDS in modern days could come with multiple capabilities. įigure 1 shows the basic DDS block diagram. As time flies by, many researchers start to explore into a possibility to implement the frequency synthesizer digitally, and there the direct digital synthesizer (DDS) was introduced. As a result, the released product is often found to be bulky and expensive considering the tight tolerance and accuracy requirement. During the beginning, there were not many options or topologies available in designing one. Many mature products in the market utilize PLL frequency synthesizer to provide a referencing element either in radio frequency or digital application. Thus, a proper reconstruction filter design will be delivered to ensure the jitter and phase noise performance is met without degrading the existing specification by taking accountability into the matching characteristic and signal integrity. Eventually the receiver quality will be degraded and resulted in tremendous loss. If they are not properly defined, the overall signal-to-noise ratio (SNR) at the sampled system output will be impacted. The key parameters in the sampled system greatly rely on the jitter and phase noise specification. This chapter will focus on the DDS selection, architecture topology, prototyping, implementation technique with both hardware and software, and performance as a clock source to a sampled system as referred to receiver interest. In recent years, the direct digital synthesizer (DDS) has been popularly in used to replace the PLL architecture. The old design may be bulky and subject to many issues with the components’ variation and aging effect. As to support its capability, phase-locked loop (PLL) frequency synthesizer has been designated as an essential part in most of the design within the box. A requirement of multiple format standards by mobile telecommunication (GSM, CDMA, WCDMA, and TD-SCDMA) test set needs to be delivered possibly at lower cost.
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